The Gigawatt AI Data Center Era

Andy Bechtolsheim, Chief Architect and Co-Founder, Arista

The design of next generation AI Data centers that are pushing to 1 Gigawatt and beyond is a major challenge from a power, cooling, and time to market perspective. This talk discusses best practices to build such data centers in an efficient fashion that minimizes time, resources, and the impact on the environment.

Scale Across: To "Go Forward" or to "Go Backwards"? That Is the Question

Tom Emmons, Software Engineer, Arista; Jai Kumar, Distinguished Engineer, Broadcom

Explore the telemetry and congestion-control challenges created by geographically distributed AI fabrics, including whether fabric-state signals should travel forward, backward, or through a hybrid model.

SUE-T – An Ethernet Transport for Scale-Up Networking

Tom Emmons, Software Engineer, Arista; Karen Schramm, VP of Architecture, Broadcom

A technical look at the Scale-up Ethernet Transport (SUE-T) framework for low-latency, high-bandwidth XPU scale-up networks and how it supports memory transactions across Ethernet-based fabrics.

Multi-Planar AI Scale-Out Fabrics

Alan Judge, Distinguished Engineer, Head of Cloud and AI, Arista; Devang Patel, Network Architect, AMD

A joint AMD and Arista discussion of open, standards-based multi-plane scale-out architectures, including OCP form factors, network design, failure handling, load balancing, cabling, AI NICs, and MRC.

Network Configurations for Optimal AI Fabrics including MRC and SRv6

Arihant Jain, Product Manager, Arista; Mohammed Hanif, Sr. Director, Engineering, Broadcom

An open, standards-based approach to scalable Ethernet AI fabrics using multi-plane leaf-spine architectures, MRC, and SRv6 for path control, deterministic load balancing, monitoring, and fast failover.

System-Level Evaluation of XPO for High-Density Optical Interconnects in AI Infrastructure

Sunil Priyadarshi, Sr. Director, Arista; Daniel Mohaghegh, Hardware Engineer, Microsoft

A joint system-level evaluation of the emerging XPO optical form factor, including testing across SerDes implementations and LPO, LRO, and FRO module types to assess interoperability, signal integrity, BER, and channel sensitivity.

Deep Buffers: The Essential Foundation for Scalable AI Training and Inference Infrastructure

Thursday, October 15, 12:30 pm – 12:45 pm | SJCC – Concourse Level – 210AE

Hugh Holbrook, Chief Development Officer, Arista; Golan Schzukin, Fellow, Broadcom

Learn why deep buffering becomes increasingly important as AI fabrics extend across regional distances, and how hybrid buffering, intelligent NIC agents, and congestion-control mechanisms can protect throughput and job completion times.

AI-Ready Network Infrastructure: The Practical Realities of High-Power, Liquid-Cooled Rack Integration

Arihant Jain, Product Manager, Arista; Rob Nance, Director of Technology, Jabil

A practical examination of what it takes to integrate and deploy AI-ready networking racks at hyperscale, including liquid cooling, high power density, optical connectivity, supply chain coordination, and repeatable factory integration.